7.9
High
CVE-2025-0647 In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when…
Description
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Affected products and versions
| Product | Affected versions | Fixed in |
|---|---|---|
| Neoverse-N2 | 0 | No fix stated |
| Neoverse-V3AE | 0 | No fix stated |
| Neoverse-V3 | 0 | No fix stated |
| Neoverse-V2 | 0 | No fix stated |
| Cortex-X925 | 0 | No fix stated |
| Cortex-X4 | 0 | No fix stated |
| Cortex-X3 | 0 | No fix stated |
| Cortex-X2 | 0 | No fix stated |
| Cortex-A710 | 0 | No fix stated |
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| Product | Affected versions | Fixed in |
|---|---|---|
| C1-Premium | 0 | No fix stated |
| C1-Ultra | 0 | No fix stated |
References
- developer.arm.com developer.arm.com
Timeline
- Published
- Last modified